Tutorial 10: Processor Part 2
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.. include:: shared/notformark.rst




Question 1
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Consider the  arm instruction :code:`ADD R3, R4, #10`.
For this instruction, find the control signals of each stage similar to slide 38 of lecure 6, which only shows stage 1, but we want to have all the signals for all the stages, for all control signals appearing on slide 34 -- 36





Question 2
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Given the set of instructions below, answer the following:


1. Indentify the data dependencies.
2. Draw a time diagram showing the clock cycles each pipelined stage takes for each instruction (see slide #50 in lecture #6), in the following two scenarios:  

 * The processor has no forward paths.
 * The processor has a forward path from :code:`Rz` to the input of the ALU and another path from :code:`Ry` to the input of the ALU.

.. code-block:: arm

 ADD R1, R2, R3
 SUB R5, R1, R4
 LDR R6, [R7]
 LSL R8, R6, #1